This invention relates to the architecture of digital memories and digital computers as integrated on a single substrate--such as a semiconductor chip or wafer.
A continual problem in this field which the integrated circuits (IC) industry faces year after year is how to integrate more and more circuitry onto the substrate. Each year, millions of dollars in research are spent by the industry on this problem. And as a result, digital memories have advanced over the years from 64 bits/chip to 65,000 bits/chip; and digital computers--the smallest of which was once comprised of thousands of chips--are now packaged on a single chip.
Two techniques have been utilized to achieve this advancement in the art. They are making the area of the chips larger, and making the individual circuit components (e.g. transistors) smaller. Over the last ten years, for example, chip areas have increased from 150.times.150 mils.sup.2 to 300.times.300 mils.sup.2 ; and FET transistor channel lengths have decreased from 8 um to less than 2 um.
Presently, the IC industry is spending additional millions of dollars on research to further increase the amount of circuitry on a chip by further increasing chip size. But as chip size is increased, yield rapidly decreases in a nonlinear fashion. For example, a process with 200.times.200 mils.sup.2 chips having a 20% yield could be expected to have a yield of near 0% on chips of 400.times.400 mils.sup.2.
This is because non-defective chips occur randomly in a wafer. Thus, doubling the sides of a 200.times.200 mil.sup.2 chip in a particular process is equivalent to accepting only sets of four non-defective 200.times.200 mils.sup.2 chips that occur side by side. But since the defect-free 200.times.200 mils.sup.2 chips occur at random, the probability of having four of them occur side by side is near 0%.
To overcome this problem, the IC industry traditionally attempts to reduce the source of the defects. But this is a very complex and expensive approach because there are so many different defect sources. Also, the techniques for further reducing various particular defect sources are already being pushed to their limits.
For example, the typical number of crystalline defects in a substrate has already been reduced over the last ten years from 1,000 defects/cm.sup.2 to 50/cm.sup.2. Also, impurity concentrations for various chemicals have been refined to 99.999%. Foreign particles in clean rooms have been reduced from 1,000 particles of less than 3 um diameter per ft.sup.3 to 100 particles of less than 1 um diameter per ft.sup.3. Processing temperatures have been lowered from over 1,000.degree. C. to less than 900.degree. C. to reduce stress-induced defects. And projection aligners, have been developed to replace contact printing to reduce mask-induced defects.
Similarly, the IC industry is also spending millions of dollars each year on reducing the size of individual circuit components. But these efforts are also frustrated by multiple limitations. For example, electron-beam lithography or x-ray lithography is required to fabricate components having geometries of less than about 2 um. But these techniques are very expensive and are still in the experimental stage. Compensating for electron scattering and proximity effects still needs further work, for example.
Also, undercutting during any etching process is a major problem. This is because since lateral dimensions are small to begin with, the slightest undercutting will aggravate any narrow width electronic phenomena--such as bird-beak for example. And this in turn can render the device inoperable.
Further, reducing the area of circuit components also requires that they be scaled in the vertical direction. Junction depths, for example, need to be shrunk. But this further limits the processing temperatures--otherwise the junction depths will increase through diffusion.
Another problem which the IC industry also spends millions of dollars on each year is how to increase the operating speed of the circuits on the chips. Again, many factors limit this speed of operation. But they include, for example, the existence of parasitic capacitances between the circuit components and the substrate, and high resistivities of various doped regions in the substrate. These limitations are developed herein in greater detail in the Detailed Description.
Still another problem that is particularly associated with mask-programmable read-only memories and digital computers incorporating the same is how to reduce the time that is required to fill a particular customer's order. This is a problem because since the chips are mask-programmable, their fabrication process varies for each customer. Thus, the chips cannot be fabricated until an order is received; and also, the fabrication process becomes longer as chip areas get larger and circuit components get smaller.
Therefore, the primary object of this invention is to provide an improved architecture for digital memories and digital computers as integrated on a single semiconductor substrate which avoids all of the above problems.